06.22.15
Cadence Design Systems, Inc. and Applied Materials, Inc. announced the companies are collaborating on a development program to optimize the chemical-mechanical planarization (CMP) process through silicon characterization and modeling for advanced-node designs at 14 nanometer (nm) and below.
The program allows design teams to predict the impact of CMP on both functional yield and parametric yield, and for manufacturing teams to boost planarization performance, which is increasingly critical for advanced FinFET architectures.
The Cadence and Applied Materials joint development program is focused on front end-of-line (FEOL) and wafer-level CMP modeling. Applied Materials can use the Cadence CMP Process Optimizer, a tool that allows silicon calibration of semi-physical models and optimization of CMP material and process parameters such as pressure, polish time and overall CMP uniformity, to enhance the precision performance of its Reflexion LK Prime CMP system.
Once models are calibrated, design teams can leverage Cadence CMP Predictor, a tool that enhances design performance and yield through model-based CMP hotspot detection and CMP-aware RC extraction. It provides full-chip, multi-level CMP thickness and topography predictions for shallow trench isolation (STI) and replacement metal gate (RMG) CMP processes.
“From our collaboration, we expect to more accurately predict gate height, dishing and erosion on each step of the CMP process, which could enable design and manufacturing teams to achieve higher yield and deliver advanced-node designs to market faster,”
said,” said Derek Witty, VP and GM of the CMP Products Group at Applied Materials.
The program allows design teams to predict the impact of CMP on both functional yield and parametric yield, and for manufacturing teams to boost planarization performance, which is increasingly critical for advanced FinFET architectures.
The Cadence and Applied Materials joint development program is focused on front end-of-line (FEOL) and wafer-level CMP modeling. Applied Materials can use the Cadence CMP Process Optimizer, a tool that allows silicon calibration of semi-physical models and optimization of CMP material and process parameters such as pressure, polish time and overall CMP uniformity, to enhance the precision performance of its Reflexion LK Prime CMP system.
Once models are calibrated, design teams can leverage Cadence CMP Predictor, a tool that enhances design performance and yield through model-based CMP hotspot detection and CMP-aware RC extraction. It provides full-chip, multi-level CMP thickness and topography predictions for shallow trench isolation (STI) and replacement metal gate (RMG) CMP processes.
“From our collaboration, we expect to more accurately predict gate height, dishing and erosion on each step of the CMP process, which could enable design and manufacturing teams to achieve higher yield and deliver advanced-node designs to market faster,”
said,” said Derek Witty, VP and GM of the CMP Products Group at Applied Materials.